{
    "@odata.type": "#Port.v1_11_0.Port",
    "Id": "1",
    "Name": "CXL Port 1",
    "Description": "CXL Port in CPU connected to CXL switch",
    "Status": {
        "State": "Enabled",
        "Health": "OK",
        "HealthRollup": "OK"
    },
    "PortId": "1",
    "RemotePortId": "4C-1D-96-FF-FE-DD-D8-D0",
    "PortProtocol": "CXL",
    "CurrentProtocolVersion": "2.0",
    "CapableProtocolVersions": [
        "1.1",
        "2.0"
    ],
    "PortType": "DownstreamPort",
    "PortMedium": "Optical",
    "CurrentSpeedGbps": 512,
    "Width": 16,
    "MaxSpeedGbps": 512,
    "ActiveWidth": 16,
    "LinkState": "Enabled",
    "LinkStatus": "LinkUp",
    "InterfaceEnabled": true,
    "LinkNetworkTechnology": "PCIe",
    "Links": {
        "AssociatedEndpoints": [
            {
                "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I1"
            },
            {
                "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I2"
            },
            {
                "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/I3"
            }
        ],
        "ConnectedSwitches": [
            {
                "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL"
            }
        ],
        "ConnectedSwitchPorts": [
            {
                "@odata.id": "/redfish/v1/Fabrics/CXL/Switches/CXL/Ports/U1"
            }
        ]
    },
    "@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU/Ports/1",
    "@Redfish.Copyright": "Copyright 2014-2023 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright."
}