{
    "@odata.type": "#Processor.v1_20_1.Processor",
    "Id": "FPGA",
    "Name": "FPGA with cache",
    "Description": "FPGA with cache accessible through CXL fabric",
    "ProcessorType": "FPGA",
    "Status": {
        "State": "Enabled",
        "Health": "OK",
        "HealthRollup": "OK"
    },
    "ProcessorMemory": [
        {
            "IntegratedMemory": true,
            "MemoryType": "Cache",
            "CapacityMiB": 64
        }
    ],
    "MemorySummary": {
        "TotalMemorySizeMiB": 0,
        "TotalCacheSizeMiB": 64
    },
    "Links": {
        "PCIeFunctions": [
            {
                "@odata.id": "/redfish/v1/Chassis/PooledCXLType1/PCIeDevices/1/PCIeFunctions/1"
            }
        ],
        "FabricAdapters": [
            {
                "@odata.id": "/redfish/v1/Chassis/PooledCXLType1/FabricAdapters/1"
            }
        ],
        "Endpoints": [
            {
                "@odata.id": "/redfish/v1/Fabrics/CXL/Endpoints/T1"
            }
        ]
    },
    "@odata.id": "/redfish/v1/Chassis/PooledCXLType1/Processors/FPGA",
    "@Redfish.Copyright": "Copyright 2014-2023 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright."
}